====EIM接口介绍====
EIM接口由驱动[[https://github.com/digi-embedded/linux/blob/v4.1/dey-2.2/maint/drivers/bus/imx-weim.c|imx-weim]]控制。在DEY中有关[[https://github.com/digi-embedded/linux/blob/v4.1/dey-2.2/maint/Documentation/devicetree/bindings/bus/imx-weim.txt|EIM接口设备树绑定的文档]]描述了如何配置它。

在很多情况下，EIM被用于同FPGA快速交换数据。为了更好地理解这一接口，我们先了解一下内存映射(mmap)。  \\
**内存映射设备操作**  \\
mmap操作提供了一种机制，让用户程序直接访问设备内存.在设备树中，内存映射设备不同于普通CPU节点，它被分配为所对应的一系列地址。#size-cells用来声明 ... 未开始...

这里有个例子，是有关如何在设备树文件中将NOR flash映射到EIM总线当中。
<code>
&weim {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>;
	#address-cells = <2>;
	#size-cells = <1>;
	ranges = <0 0 0x50000000 0x08000000>;
	status = "disabled"; /* pin conflict with qspi, nand and lcd1 */

	nor@0,0 {
		compatible = "cfi-flash";
		reg = <0 0 0x02000000>;
		#address-cells = <1>;
		#size-cells = <1>;
		bank-width = <2>;
		fsl,weim-cs-timing = <0x00610081 0x00000001 0x1c022000
0x0000c000 0x1404a38e 0x00000000>;
	};
};


&iomuxc {
	weim {
		pinctrl_weim_cs0_1: weim_cs0grp-1 {
			fsl,pins = <
				MX6SX_PAD_NAND_ALE__WEIM_CS0_B       0xb0b1
			>;
		};

		pinctrl_weim_nor_1: weim_norgrp-1 {
			fsl,pins = <
				MX6SX_PAD_NAND_CE1_B__WEIM_OE        0xb0b1
				MX6SX_PAD_NAND_RE_B__WEIM_RW         0xb0b1
				MX6SX_PAD_NAND_WE_B__WEIM_WAIT       0xb060
				/* data */
				MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0   0x1b0b0
				MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1  0x1b0b0
				MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2  0x1b0b0
				MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3  0x1b0b0
				MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4  0x1b0b0
				MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5  0x1b0b0
				MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6  0x1b0b0
				MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7    0x1b0b0
				MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8   0x1b0b0
				MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9  0x1b0b0
				MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x1b0b0
				MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x1b0b0
				MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x1b0b0
				MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x1b0b0
				MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x1b0b0
				MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15   0x1b0b0
				/* address */
				MX6SX_PAD_NAND_DATA00__WEIM_AD_0     0xb0b1
				MX6SX_PAD_NAND_DATA01__WEIM_AD_1     0xb0b1
				MX6SX_PAD_NAND_DATA02__WEIM_AD_2     0xb0b1
				MX6SX_PAD_NAND_DATA03__WEIM_AD_3     0xb0b1
				MX6SX_PAD_NAND_DATA04__WEIM_AD_4     0xb0b1
				MX6SX_PAD_NAND_DATA05__WEIM_AD_5     0xb0b1
				MX6SX_PAD_NAND_DATA06__WEIM_AD_6     0xb0b1
				MX6SX_PAD_NAND_DATA07__WEIM_AD_7     0xb0b1
				MX6SX_PAD_LCD1_DATA08__WEIM_AD_8     0xb0b1
				MX6SX_PAD_LCD1_DATA09__WEIM_AD_9     0xb0b1
				MX6SX_PAD_LCD1_DATA10__WEIM_AD_10    0xb0b1
				MX6SX_PAD_LCD1_DATA11__WEIM_AD_11    0xb0b1
				MX6SX_PAD_LCD1_DATA12__WEIM_AD_12    0xb0b1
				MX6SX_PAD_LCD1_DATA13__WEIM_AD_13    0xb0b1
				MX6SX_PAD_LCD1_DATA14__WEIM_AD_14    0xb0b1
				MX6SX_PAD_LCD1_DATA15__WEIM_AD_15    0xb0b1
				MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16  0xb0b1
				MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17  0xb0b1
				MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18  0xb0b1
				MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19  0xb0b1
				MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20  0xb0b1
				MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21  0xb0b1
				MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22  0xb0b1
				MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24  0xb0b1
				MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25  0xb0b1
				MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26  0xb0b1
			>;
		};
	};
};



</code>